In integrated dynamic memories such as DRAMs, a refresh operation is necessary during operations in which memory cells are not accessed external, in order to refresh the memory cell content, which can volatilize, for example, due to leakage currents of the storage capacitor or selection transistor, and thus to permanently retain the memory cell content. During the refresh operation, the assessed and amplified data signals from selected memory cells are written back directly to the relevant memory cells. This is generally controlled by a controller circuit, which defines a refresh frequency with which a respective refresh of the memory cell content is effected.
There are a number of possibilities for refreshing the content of memory cells. Firstly, during a normal operation of the memory for carrying out read or write operations, as early as with the activation of a word line of the memory and with the subsequent closing of the word line, the information read from the relevant memory cells is assessed and amplified in sense amplifiers. The assessed and amplified information is written back to the memory cells and refreshed in this way, i.e., normal activate-precharge cycle.
Furthermore, the memory controller sends auto-refresh commands to the memory, which in each case initiate a command sequence for activating a row due for refreshing. For example, a refresh counter defines which of the rows is due for refreshing. The refresh counter successively addresses the rows of the dynamic memory, for example, in a sequential sequence of their addresses. Such a refresh process is often effected in parallel in the memory banks of the memory such that a row is in each case activated and closed again simultaneously in each memory bank. If a memory bank has 4096 rows, for example, the memory controller that drives the memory sends an autorefresh command to the memory every 64 ms/4096 (the data retention time is 64 ms), for example.
For data retention, the memory may enter a self-refresh mode, in which a refresh counter periodically internally initiates a command sequence for activation and for closing of a row of the memory, similarly to an auto-refresh command described previously. The data of memory cells can thus be refreshed regularly even without an external auto-refresh command of a memory controller.
A memory controller, which controls access to the dynamic memory has the task, inter alia, of ensuring that none of the rows of the memory is in the non-activated state for longer than the maximum specified data retention time, for example 64 ms. In the simplest case, the memory controller intersperses an auto-refresh command between the normal read and write operations on average every 15.6 μs (=64 ms/4096). The term used in this case is distributed refreshes, which can be implemented only when the memory is not in a read or write mode.
With this type of distributed refresh, in particular, it is not possible to define when a distributed refresh is to be effected, since the points in time depend on the access capacity utilization. A high access capacity utilization during read and write operations of the memory would mean, however, that a multiplicity of rows are opened and closed again anyway during active operation, so that the information items are already refreshed during the customary read and write operations. In this case, the autorefresh commands are sent to the memory as a precaution in a regular sequence in a supporting manner, without knowing the actual refresh status.